主题：VLSI Optimization for Deep Neural Networks
专家：王中风教授，国家特聘专家，南京大学电子科学与工程学院
时间：2021年4月8日 下午14:30-16:00
地点：博万通娱乐 B222
摘要：
Following a brief introduction to VLSI Signal Processing, we will first present a new architecture of CNN inference accelerator based on fast convolution algorithm and dynamic computing flow, then discuss the hardware design optimization of GAN based on algorithmic transformation, and an optimized architectural design for reconfigurable convolution-deconvolution operations. Thereafter, I will introduce some of the latest achievements of our research group, including a reconfigurable and scalable sparsity-aware CNN inference architecture, and a hardware-efficient DNN training algorithm as well as its associated architectural design based on a new data format.
专家简介：
Dr. Zhongfeng Wang received both BS and MS degrees from Tsinghua University. He obtained the Ph.D. degree from the University of Minnesota, Minneapolis, in 2000. He has been working for Nanjing University, China, as a Distinguished Professor since 2016. Previously he worked for Broadcom Corporation, California, from 2007 to 2016 as a technical director. Before that, he worked for Oregon State University and National Semiconductor Corporation successively.
Dr. Wang is a world-recognized expert on Low-Power High-Speed VLSI Design for Signal Processing Systems. He has published over 250 technical papers with six best paper awards received from IEEE, including Circuits and Systems (CAS) society VLSI Transactions Best Paper Award in 2007. He has edited one book “VLSI” and held tens of U.S. and China patents. In the current record, he has had nearly ten papers ranked among (annually) top 25 downloaded manuscripts in IEEE Trans. on VLSI Systems. In the past, he has served as Associate Editor for IEEE Trans. on CAS-I, CAS-II, and VLSI Systems for many terms. Meanwhile, he has contributed significantly to the industrial standards. So far, his technical proposals have been adopted by more than fifteen international networking standards. In 2015, he was elevated to the Fellow of IEEE for contributions to VLSI design and implementation of FEC coding. His current research interests are in the area of Optimized VLSI Design for Digital Communications and Deep Learning.
